Power budget of Xilinx based on FPGA
Power budget of Xilinx based on FPGA
Let's make a Xilinx power budget.
There are two methods of power budget commonly used by fpgamall.com
1. For the power budget before design:
for the initial chip selection of the scheme, if the scheme has great requirements for power consumption, the first step is to estimate and evaluate the power consumption of the chip, so as to judge whether the chip meets the requirements of the scheme. Of course, the selection of the chip depends not only on the power consumption, but also on the resources. Prepare for the next chapter to summarize the selection of resources (only in this way, specific I'll talk about what to write next.2. For the power budget in the scheme:
if the scheme has been basically determined and the program is almost written, the premise is that most of the resources of the whole program have been written, and the always constraint and pin constraint have been written. Salinix can directly estimate the power consumption through ISE or vivado.Today, I will mainly talk about the first budget method and the second one.
1. For the power budget of design money:
For the pre design power budget, the premise is to know the overall amount of resources to be used, that is, first of all, we should have a general understanding of the overall resource utilization, and then budget the power consumption of different chips when the resources are sufficient according to the resource utilization.
The full name of FPGA is large-scale programmable logic matrix, and the power consumption is the energy consumption per unit time, which leads to the corresponding problems: 1) the power consumption is related to the internal reference clock of FPGA. The faster the power consumption is, the faster the flip-flop speed will be in unit time. There is also the inversion probability, that is, how many% of the flip-flops have to be reversed. This is to know Why should we know the reference clock and reverse rate in the program. 2) Most of the power consumption in FPGA is on flip flops. In general, flip flops are used most, so the number of internal devices such as flip flops should be considered.
According to the above description, we know that to make the power budget before design, we must first have a framework for the overall clock of the system, and then have a framework for the overall resource consumption. I first wrote a program. The basic function of the program is the target function, that is, the resource consumption is almost the same. However, there is no pin constraint and clock constraint. After synthesis, the bitstream file is reported as an error, but it does not affect the allocation of resources by ISE.
All right, no more nonsense. Let's get some dry goods. Go straight http://china.xilinx.com/products/design_ resources/power_ Central / download the excel table corresponding to the chip model to budget power consumption. Here we have to say the powerful function of Excel. It's really too strong. I admire it!
After downloading, you should first open the macro permission of local excel. Take office2007 as an example:XC2V1000-4FG456IClick excel options, and then XCZU7EG-1FBVB900E Click Trust Center settingsXC7Z045-2FFG676I
If the above situation is selected, it is OK.
Then restart excel and open the downloaded form,
This is my final budget result, ignoring the results on the table. It's at the bottom
Fill in the clock, logic, IO, Bram, DSP and other modules according to the usage budget, and then look at the summary power consumption.
According to the comprehensive summary, I fill in the table according to each classification and automatically get the above results.
This is just a simple estimate. Theoretically speaking, there should be little deviation.
2. Power consumption estimation in design
Visual inspection is in the design, after the comprehensive wiring of the program is completed, open xpower directly and come out After comparison, it was found that the power consumption error was in IO port, PLL, MMCM, and Bram. Because this part belongs to the hard core part, the data manual was not read carefully, and the hard core such as PLL and MMCM was not filled in (the power consumption of PLL and MMCM was very large!).
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